1. Field of the Invention
The present invention relates to a level conversion circuit, and in particular, relates to duty correction in level conversion of a clock signal.
2. Description of the Prior Art
Semiconductor integrated circuits are required to respond to a high speed operation and a multi-function. With the advancement of the semiconductor technology, a large number of circuit blocks are formed on a single chip, and optimum circuits are constituted for functions to be provided. For this reason, multiple signal levels are often present in the semiconductor integrated circuit. With the high speed operation, in particular, differential interfaces or unbalance interfaces are used for signal transmission. Since a signal of a single end type is usually used in a logic circuit section, a signal level conversion circuit is required in interface between circuit blocks.
Logic circuits often include synchronous circuits, and a clock signal is especially important as the reference of signal timing. Therefore, duty degradation needs to be controlled. However, the duty degradation is caused by relative variations of process level and characteristics, and has great effect on performance degradation of the synchronous circuits. Particularly, there is a possibility that the duty degradation is greater in a long clock line and so on. Therefore, it is desired to perform duty correction in a last stage and to use a clock signal with the duty ratio close to 50% in the synchronous circuits.
In high-speed circuits that transmission rate exceeds the order of GHz, a CML (Current Mode Logic) signals as small-amplitude differential signals with high noise tolerance, are often used in a long clock line and so on. A CML level clock signal is level-converted into a CMOS logic level signal in the last stage, and is used in synchronous circuits of a CMOS configuration in many cases. Level conversion circuits becomes complex in circuit configuration, and are easy to cause duty degradation because of the influence of the relative variations of the process level and characteristics compared with circuits for the small-amplitude differential signals.
A level conversion circuit for clock signals is disclosed in Japanese Laid Open Patent Application (JP-P2000-305528A), for example. The conventional level conversion circuit is provided with a level converting section 21 and a cross-point correction section 22, as shown in FIG. 1. The level converting section 21 performs level conversion, converting a clock signal of a first signal level (e.g., the level of a CML signal as a small-amplitude differential signal) into a clock signal of a second signal level (e.g. the CMOS logic level). The clock signal of the second signal level is supplied to the cross-point correcting section 22 for cross-point correction. The cross-point correcting section 22 is provided with inverters 25 to 28, and performs the cross-point correction such that the duty ratio of two-phase clock signals of the second signal level is 50 percent.
FIGS. 2A to 2E show examples of signal waveforms at nodes N1 and N2 to which input signals of the first signal level are applied, at output nodes N7 and N8 of the level converting section 21, and at output nodes N9 and N10 of the cross-point correction section 22. As shown in FIG. 2A, differential signals of sine waveforms are supplied to the input nodes N1 and N2. When the characteristics of the level converting section 21 match with positive phase and reverse phase signals, the output of the level converting section 21 (the nodes N7 and N8) is a clock signal with the duty ratio of 50%, as shown in FIG. 2B. As a result, the clock signal with the duty ratio of 50% is also outputted to the nodes N9 and N10 as well.
When the second signal level is a signal level in which variations are liable to occur in rising and falling characteristics of signals, as in case of the CMOS logic level, signals at the nodes N7 and N8 may have the duty ratio of (50±α)% as shown in FIG. 2C. In this case, the duty ratio is 50% at a voltage where the signals of the nodes N7 and N8 intersect, and the duty correction is then performed by the cross-point correction section 22, and signals with the duty ratio of 50% are supplied to the nodes N9 and N10.
However, when a normal mode offset occurs to input signals as shown in FIG. 2D, signal waveforms at the nodes N7 and N8 do not show the duty ratio of 50% even at cross points in many cases. In these cases, improvement of the duty ratio is not possible even when the cross-point correction is performed by the cross-point correction section 22, where signals at the nodes N9 and N10 show the duty ratios of (50±β)%, as shown in FIG. 2E.
The duty correction is thus possible by utilizing a reverse-phase signal, when the cause of duty degradation affects a common mode in differential signals. However, when a normal mode is affected, namely when the differential signals are imbalanced, the duty correction is not possible even by utilizing the reverse-phase signal.
In conjunction with the above description, Japanese Laid Open Patent Application (JP-P2001-156597A) discloses a technique to adjust a duty ratio of output of a voltage controlled oscillator circuit. A duty correcting circuit inputs a reverse output and a non-reverse output from a voltage controlled oscillator circuit. The duty correcting circuit is provided with an output adjustment section. The output adjustment section outputs output waveform signals in which a low level pulse width for a pulse period of the reverse output and a high level pulse width for a pulse period of the non-reverse output are equal. This output adjustment section is an RS flip-flop to input the reverse output and the non-reverse output of the voltage controlled oscillator circuit.